The Compilation Gap
Transformers don't run on silicon—they run on abstractions. The compiler translates high-level logic into instructions, but those instructions must traverse the bridge between software and hardware. Most systems treat this as an implementation detail. We treat it as a boundary worth defending.
THE SOVEREIGN PATH
TypeScript → SIR → Trinity → Silicon. Four transformations. Each one preserves provenance. Each one generates a hash. The output is not just computation—it is computation with a verifiable history.
SIR Instruction Types
The Sovereign Intermediate Representation defines a minimal instruction set optimized for heterogeneous hardware. Each instruction carries implicit theater routing—knowledge of where it should execute for optimal performance.
| Instruction | Description | Optimal Theater | Why |
|---|---|---|---|
| SIR_ADD | Floating-point addition | iGPU | Parallel addition, unified memory zero-copy |
| SIR_MUL | Floating-point multiplication | dGPU | Massive parallel throughput |
| SIR_NEG | Negation (-x) | iGPU | Fast inverse operation |
| SIR_DIV | Division | dGPU | Compute-intensive |
| SIR_MATMUL | Matrix multiplication | dGPU | High-throughput compute |
Data Flow
Every piece of data that traverses the SIR → Trinity bridge carries its provenance. The bridge doesn't just route instructions—it timestamps them, hashes them, and records which theater executed what.
User-defined logic. The origin of computation.
Lexer → Parser → SIR Emitter. Language to representation.
Platform-agnostic intermediate representation.
Routes to optimal theater based on instruction type.
Hardware-bound execution. iGPU or dGPU.
Blake3(instruction || input || output). Cryptographic proof.
Provenance Tracking
Each SIR execution produces a complete provenance record:
- Input hash — Blake3 of input tensors
- Instruction hash — Blake3 of SIR opcode
- Output hash — Blake3 of output tensors
- Theater ID — iGPU or dGPU, not vague "GPU"
- Timestamp — Nanosecond precision
Theater Assignment Rules
The Trinity Router maintains assignment rules optimized for each instruction type:
| SIR Instruction | Primary Theater | Fallback |
|---|---|---|
| SIR_ADD | iGPU | CPU |
| SIR_MUL | dGPU | iGPU |
| SIR_NEG | iGPU | CPU |
| SIR_DIV | dGPU | iGPU |
| SIR_MATMUL | dGPU | iGPU |
| SIR_LOAD | CPU | — |
| SIR_STORE | CPU | — |
What Remains Hidden
The exact kernel implementations—the actual compute shaders that execute on iGPU and dGPU—remain within the protected core. We present the bridge architecture, the routing rules, and the provenance system. The execution engines themselves are the sauce that cannot be disclosed.
What flows through this bridge is not merely computation. It is computation with identity. Each instruction carries its history from TypeScript source to silicon execution. The hash at the end is not a byproduct—it is the proof.