The Routing Problem
Heterogeneous compute requires intelligent routing. A CPU excels at sequential logic. An integrated GPU offers unified memory bandwidth. A discrete GPU provides raw compute density. Naive parallelization—sending any operation to any available hardware—creates friction, thermal imbalance, and wasted cycles.
THE SOVEREIGNTY INSIGHT
Operations have affinity. Memory-intensive work flows to hardware with bandwidth. Compute-intensive work routes to hardware with cores. Control-flow remains on the CPU. This is not load balancing—it is computational topology.
The Three Lanes
SIR Executor defines three computational lanes, each with distinct hardware affinity:
| Lane | Hardware | Affinity | Operations |
|---|---|---|---|
| TimeLane | CPU (Ryzen 5) | Control-flow, sequencing | Tokenization, routing decisions |
| DensityLane | iGPU (Vega 7) | Memory bandwidth | Dequantization, embedding lookup |
| SpaceLane | dGPU (GTX 1650) | Compute density | Attention, matrix multiplication |
Lane Routing in Practice
When SIR encounters an operation, it routes based on computational characteristics:
- SIR_LOAD / SIR_STORE — TimeLane (CPU). Memory management requires sequential consistency.
- SIR_DEQUANT — DensityLane (iGPU). Bandwidth-intensive weight expansion benefits from unified memory.
- SIR_MATMUL — SpaceLane (dGPU). Compute-intensive matrix operations leverage tensor cores.
- SIR_ATTENTION — SpaceLane (dGPU). Attention mechanisms are inherently parallel.
Provenance Tracking
Every routed operation leaves a trace in lane_ledger.jsonl:
- op_name — The operation performed
- lane — Which lane executed it
- instruction_hash — Blake3 of the SIR instruction
- parent_hashes — Dependencies that preceded this operation
- genesis_hash — Hardware-bound identity of execution
- timestamp — When it occurred
- output_hash — Result verification
This provenance chain enables complete auditability. Every result can be traced back through its execution path, verified against the hardware that produced it.
What Remains Hidden
The exact routing algorithms—the decision thresholds, the thermal integration, the fallback mechanisms when lanes are saturated—remain within the protected core. We present the architecture: three lanes, distinct affinities, provenance tracking. The routing intelligence itself is the sauce.