The Trinity had three theaters. CPU, iGPU, dGPU. But the river that connected them—RAM—had never been measured. It was assumed. Guessed at. Treated as a given. In Layer 20, we finally benchmarked the fourth theater.
The Missing Theater
RAM is not storage. RAM is the Theta-Link—the memory fabric that connects CPU, iGPU, and dGPU into a unified computational topology. Every weight load passes through it. Every KV cache write touches it. Yet we'd never formally tested how it performed under various configurations.
Six kernels. Multiple configurations. 120 samples. Real hardware measurements from /proc/meminfo, /proc/vmstat, and direct timing. No simulation. No estimation.
Kernels Tested
We implemented six distinct memory operations:
- Sequential read (100MB linear)
- Sequential write (100MB linear)
- Random read (1M 64-byte accesses)
- Random write (1M 64-byte accesses)
- Memcpy (256MB block transfer)
- Page fault stress (10K page touches)
Results
Configuration Differentiation
Each configuration produced measurably different results. Some configurations favored sequential access. Others excelled at random access patterns. The routing scheduler now has real data to make decisions—not assumptions.
The River Has Depth
Before this work, RAM was a black box. Now it's a measured, characterized theater with known performance signatures under various configurations. The Trinity is complete. Four theaters. All benchmarked. All verified.
Evidence file: evidence/silicon_primals/ram_silicon_results_*.jsonl — 120 samples.